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FEATURES Pin Selectable 1- or 2-Phase Operation Static and Dynamic Current Sharing Characteristics Backward Compatible to IMVP-II Superior Load Transient Response with ADOPTTM Optimal Positioning Technology Noise Blanking for Speed and Stability Synchronous Rectifier Control Extends Battery Life Smooth Output Transition During VID Code Change Cycle-by-Cycle Current Limiting Hiccup or Latched Overload Protection Transient Glitch-Free Power Good Soft Start Eliminates Power-On In-Rush Current Surge 2-Level Overvoltage and Reverse Voltage Protection APPLICATIONS IMVP-II and IMVP-III Core DC-to-DC Converters Fixed Voltage Mobile CPU Core DC-to-DC Converters Notebook/Laptop Power Supplies Programmable Output Power Supplies
2-Phase IMVP-II and IMVP-III Core Controller for Mobile CPUs ADP3203
FUNCTIONAL BLOCK DIAGRAM
VCC
ADP3203
HYSSET DSHIFT BSHIFT HYSTERESIS SETTING AND SHIFT-MUX VR
PHASE SPLITTER
OUT2 OUT1 CS2
CLIM
CS1 CURRENT SENSE MUX
CORE
CS+ CS- RAMP REG
EN
VID4
GENERAL DESCRIPTION
VID3 VID2 VID1 VID0 BOM DSLP
The ADP3203 is a 1- or 2-phase hysteretic peak current dc-to-dc buck converter controller dedicated to power a mobile processor's core. The optimized low voltage design is powered from the 3.3 V system supply and draws only 10 A maximum in shutdown. The nominal output voltage is set by a 5-bit VID code. To accommodate the transition time required by the newest processors for on-the-fly VID changes, the ADP3203 features high speed operation to allow a minimized inductor size that results in the fastest change of current to the output. To further allow for the minimum number of output capacitors to be used, the ADP3203 features active voltage positioning with ADOPT optimal compensation to ensure a superior load transient response. The output signal interfaces with the ADP3415 MOSFET driver that is optimized for high speed and high efficiency for driving both the top and bottom MOSFETs of the buck converter. The ADP3203 is capable of controlling the synchronous rectifier to extend battery lifetime in light load conditions.
5-BIT VID DAC AND FIXED REF
DACOUT
VR
SD PWRGD
ENABLE _UVLO MAIN BIAS PWRGD BLANKER
SR CONTROL
DRVLSD COREFB SS CLAMP
COREGD MONITOR
DPRSLP DSLP BOM VID MUX AND SHIFT SELECTOR SS-HICCUP TIMER AND OCP OVP AND RVP PM MODULE
GND
ADOPT is a trademark of Analog Devices.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
100 C, High (H) = VCC, Low (L) = 0 V, VCC = 3.3 V, SD = H, VCOREFB = VREG = VCS- = VVID = 1.25 V, ROUT1 =ROUT2 100 k , COUT1 = COUT2 = 10 pF, CSS =0.047 F, RPWRGD = 680 to 1.2 V, RCLAMP = 5.1 k to VCC; HYSSET, BSHIFT, DSHIFT, and DPRSHIFT are open; BOM = H, DSLP = H, DPRSLP = L, unless otherwise noted.) Current sunk by a pin has a positive sign, sourced by a pin has a negative sign. Negative sign is disregarded for min and max values.
A DAC DACOUT),
ADP3203-SPECIFICATIONS1 (0 C (0 VT V
Parameter SUPPLY-UVLO-SHUTDOWN Normal Supply Current UVLO Supply Current Shutdown Supply Current UVLO Threshold Symbol ICC ICCUVLO ICCSD VCCH VCCL UVLO Hysteresis Shutdown Threshold (CMOS Input) POWER GOOD Core Feedback Threshold Voltage VCCHYS VSDTH VCOREFBH
Conditions
Min
Typ 7
Max 9 75
Unit mA A A V V mV
VCC = 2.63 V SD = L, 3.0 V VCC 3.6 V SD = H VCC Ramping Up, VSS= 0 V VCC Ramping Down, 2.65 VSS Floating 50
10 2.95
VCC/2 0.9 V < VDAC < 1.675 V VCOREFB Ramping Up VCOREFB Ramping Down VCOREFB Ramping Up VCOREFB Ramping Down VCOREFB = VDACOUT VCOREFB = 0.8 VDACOUT
V
Power Good Output Voltage (Open-Drain Output) Masking Time SOFT START/HICCUP TIMER Charge/Discharge Current Soft Start Enable/Hiccup Termination Threshold
VPWRGD tPWRGDMSK3 ISS
1.12 VDAC 1.10 VDAC 0.88 VDAC 0.86 VDAC 0.95 VCC 0 100 -16 0.5
1.14 VDAC 1.12 VDAC 0.90 VDAC 0.88 VDAC VCC 0.8
V V V V V V s A A
Soft Start Termination/Hiccup Enable Threshold VID DAC VID Input Threshold (CMOS Inputs) VID Input Current (Internal Active Pull-Up) Output Voltage Accuracy
VSSENDWN VSSENUP4 VSSTERM
VSS = 0 V VSS = 0.5 V VREG = 1.25 V, VRAMP = VCOREFB = 1.27 V VSS Ramping Down VSS Ramping Up VRAMP = VCOREFB = 1.27 V VSS Ramping Up
80 150 1.75 2.00
200
mV mV V
2.25
VVID0..4 IVID0..4 VDAC VDAC/VDAC tDACS5
VID0 to VID4 = L See VID Code, Table I 0C TA 85C 1.75 VDAC 0.850 0.825 VDAC 0.600 VDAC = 0.5 V, CDAC = 10 nF 0.600 -0.85 -7.2
VCC/2 85 1.750 +0.85 +7.2 3.5
V A V % mV s
Settling Time
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Parameter CORE COMPARATOR Input Offset Voltage (Ramp-Reg) Input Bias Current Output Voltage (OUT1, OUT2) Propagation Delay Time Rise and Fall Time2 Noise Blanking Time CURRENT LIMIT COMPARATOR Input Offset Voltage Input Bias Current Propagation Delay Time CURRENT SENSE MULTIPLEXER Transresistance Common-Mode Voltage Range4 HYSTERESIS SETTING Hysteresis Current Symbol VCOREOS IREG, IRAMP VOUT_H VOUT_L tRMPOUT_PD6 tOUT_R7 tOUT_F7 tBLNK Conditions VREG = 1.25 V VREG = VRAMP = 1.25 V VCC = 3.0 V VCC = 3.6 V TA = 25C TA = Full Range OUT L-H Transition OUT H-L Transition Min Typ 1 1 2.5 0 35 40 7 7 130 180 3.0 0.4 Max Unit mV A V V ns ns ns ns ns ns
10 10
VCLIMOS ICS+, ICS- tCLiMPD6
VCS- = 1.25 V VCS+ = 1.25 V TA = 25 C TA = Full Range
1 -3 60 100
mV A ns ns
RCS1-CS+, RCS2-CS+, RCS3-CS+ VCS1 = VCS2 IRAMP_H, -ICSP_H
Switch Is ON Switch Is OFF 0 VREG = 1.25 V VRAMP = 1.23 V, BOM = H IHYSSET = -10 A IHYSSET = -100 A VRAMP = 1.27 V, BOM = H IHYSSET = -10 A IHYSSET = -100 A VRAMP = 1.23 V, BOM = L IHYSSET = -10 A IHYSSET = -100 A VRAMP = 1.27 V, BOM = L IHYSSET = -10 A IHYSSET = -100 A
150 50 2
M V
-8 -85 8 85 -6.4 -68 6.4 68 1.65
-10 -100 10 100 -8 -80 8 80 1.7
-12 -115 12 115 -9.6 -92 9.6 92 1.75
A A A A A A A A V
Hysteresis Reference Voltage CURRENT LIMIT SETTING Hysteresis Current
VHYSSET ICS- VRAMP = 1.23 V VREG = VCS- = VCOREFB = 1.25 V VCS+ = 1.23 V BOM = H IHYSSET = -10 A IHYSSET = -100 A VCS+ = 1.27 V, BOM = H IHYSSET = -10 A IHYSSET = -100 A VCS+ = 1.23 V, BOM = L IHYSSET = -10 A IHYSSET = -100 A VCS+ = 1.27 V, BOM = L IHYSSET = -10 A IHYSSET = -100 A
-27 -270 -18 -180 -21 -226 -14 -144
-31.5 -36 -301.5 -333 -21.5 -25 -201.5 -223 -25.5 -30 -241.5 -267 -17.5 -21 -161.5 -179
A A A A A A A A
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Parameter SHIFT SETTING Battery Shift Current Symbol IRAMPB, ICS+B VBSHIFT IRAMPD, ICS+D VDSHIFT VBOM VDSLP VDPRSLP VVID = 1.25 V IDSHIFT = -100 A, BOM = H DSLP = L -92.5 Conditions VVID = 1.25 V IBSHIFT = -100 A, BOM = L DSLP = H Min -92.5 Typ -100 Max -107.5 Unit mA
Battery Shift Reference Voltage Deep Sleep Shift Current
VDAC -100 -107.5
V mA
Deep Sleep Shift Reference Voltage SHIFT CONTROL INPUTS BOM Threshold (CMOS Input) DSLP Threshold (VTT-Level CMOS Input) DPRSLP Mode Threshold8 (CMOS Input) LOW SIDE DRIVE CONTROL Output Voltage (CMOS Output) Output Current
VDAC VCC/2 0.9 VCC/2
V V V V
VDRVLSD IDRVLSD
DPRSLP = H DPRSLP = L DPRSLP = H, VDRVLSD = 1.5 V DPRSLP = L, VDRVLSD = 1.5 V
0 0.7 VCC 0.4 -0.4
0.4 VCC
V V mA mA
OVER/REVERSE VOLTAGE PROTECTION-CORE FEEDBACK Overvoltage Threshold Reverse Voltage Threshold Output Voltage (Open-Drain Output) Output Current
VCOREFB,OVP VCOREFB,OVP VCLAMP ICLAMP
VCOREFB Rising VCOREFB Falling 0.7 VCC VCOREFB = 2.2 V, VCLAMP = 5 V VCOREFB = VDAC, VCLAMP = 5 V 2
2.0 -0.3 VCC 10 4
V V V A mA
NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 2 Guaranteed by characterization. 3 Two test conditions: 1)PWRGD is OK but forced to fail by applying an out-of-the-Core-Good-window voltage (V COREFB,BAD = 1.0 V at VVID = 1.25 V setting) to the COREFB pin right after the moment that BOM or DPRSLP is asserted/deasserted. PWRGD should not fail immediately, only with the specified blanking delay time. 2) PWRGD is forced to fail (V COREFB, BAD = 1.0 V at V VID = 1.25 V setting) but gets into the Core Good window (VCOREFB, GOOD = 1.25 V) right after the moment that BOM or DPRSLP is asserted/deasserted. PWRGD should not go high immediately, only with the specified blanking delay time. 4 Guaranteed by design. 5 Measured from 50% of VID code transition amplitude to the point where VDACOUT settles within 1% of its steady state value. 6 40 mVp-p amplitude impulse with 20 mV overdrive. Measured from the input threshold intercept point to 50% of the output voltage swing. 7 Measured between the 30% and 70% points of the output voltage swing. 8 DPRSLP circuit meets the minimum 30 ns DPRSLPVR signal assertion requirement; guaranteed by design.
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ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION
Input Supply Voltage (VCC) . . . . . . . . . . . . . . -0.3 V to +7 V All Other Inputs/Outputs . . . . . . . . . . . -0.3 V to VCC + 0.3 V Operating Ambient Temperature Range . . . . . . 0C to 100C Junction Temperature Range . . . . . . . . . . . . . . . 0C to 150C JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98C/W Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . 300C
*This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged.
HYSSET 1 DSHIFT 2 BSHIFT 3 VID4 4 VID3 5 VID2 6
28 CS- 27 CS+ 26 REG 25 RAMP
TOP VIEW 23 CS2 VID1 7 (Not to Scale) 22 CS1 VID0 8
21 OUT2 20 OUT1 19 GND 18 DACOUT 17 COREFB 16 SS 15 DRVLSD
ADP3203
24 VCC
ORDERING GUIDE
BOM 9 DPSLP 10 DPRSLP 11 PWRGD 12 SD 13 CLAMP 14
Model ADP3203JRU-0.85-RL ADP3203JRU-0.85-R7 ADP3203JRU-1.0-RL ADP3203JRU-1.0-RL7
Temperature Package Package Range Description Option 0.85 V 0.85 V 1V 1V 0C to 100C 0C to 100C 0C to 100C 0C to 100C TSSOP-28 TSSOP-28 TSSOP-28 TSSOP-28
Table I. VID Code
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
VOUT 1.750 1.700 1.650 1.600 1.550 1.500 1.450 1.400 1.350 1.300 1.250 1.200 1.150 1.100 1.050 1.000 0.975 0.950 0.925 0.900 0.875 0.850 0.825 0.800 0.775 0.750 0.725 0.700 0.675 0.650 0.625 0.600
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3203 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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PIN FUNCTION DESCRIPTIONS Pin 1 Mnemonic HYSSET Function Hysteresis Set. This is an analog I/O pin whose output is a fixed voltage reference and whose input is a current that is programmed by an external resistance to ground. The current is used in the IC to set the hysteretic currents for the core comparator and the current limit comparator. Modification of the resistance will affect both the hysteresis of the feedback regulation and the current limit setpoint and hysteresis. Deep Sleep Shift. This is an analog I/O pin whose output is the VID reference voltage and whose input is a current that is programmed by an external resistance to ground. The current is used in the IC to set a switched bias current out of the RAMP pin, depending on whether it is activated by the DPSLP signal. When activated, this added bias current creates a downward shift of the regulated core voltage to a predetermined optimum level for regulation corresponding to Deep Sleep Mode of CPU operation. The use of the VID code as the reference makes the deep sleep offset a fixed percentage of the VID setting, as required by specifications. Battery Optimized Mode (BOM) Shift. This is an analog I/O pin whose output is the VID reference voltage and whose input current is programmed by an external resistance to ground. The current is used in the IC to set a switched bias current out of the RAMP pin, depending on whether it is activated by the BOM signal. When activated, this added bias current creates a downward shift of the regulated core voltage to a predetermined optimum level for regulation corresponding to the Battery Optimized Mode of the CPU operation. The use of the VID code as the reference makes the BSHIFT a fixed percentage of the VID setting, as required by specifications. Voltage Identification Inputs. These are the VID inputs for logic control of the programmed reference voltage that appears at the DACOUT pin, and via external component configuration, is used for setting the output voltage regulation point. The VID pins have a specified internal pull-up current that, if left open, will default the pins to a logic high state. The VID code does not set the DAC output voltage directly but through a transparent latch that is clocked by the BOM pin's GMUXSEL signal rising and falling edge. Battery Optimized Mode Control (Active Low). This digital input pin corresponds to the system's GMUXSEL signal, which corresponds to Battery Optimized Mode of the CPU operation in its active low state and Performance Optimized Mode (POM) in its deactivated high state. The signal also controls the optimal positioning of the core voltage regulation level by offsetting it downward in Battery Optimized Mode according to the functionality of the BSHIFT and RAMP pins. It is also used to initiate a masking period for the PWRGD signal whenever a GMUXSEL signal transition occurs. Deep Sleep Mode Control (Active Low). This is a digital input pin corresponding to the system's STP CPU signal that, in its active state, corresponds to Deep Sleep Mode of the CPU operation, which is a subset operating mode of either BOM or POM operation. The signal controls the optimal positioning of the core voltage regulation level by offsetting it downward according to the functionality of the DSHIFT and RAMP pins. Deeper Sleep Mode Control (Active High). This is a digital input pin corresponding to the system's DPRSLPVR signal corresponding to Deeper Sleep Mode of the CPU operation. When the signal is activated, it controls the DAC output voltage by disconnecting the VID signals from the DAC input and setting a specified internal deeper sleep code instead. At deassertion of the DPRSLPVR signal, the DAC output voltage returns to the voltage level determined by the external VID code. The DPRSLPVR signal is also used to initiate a blanking period for the PWRGD signal to disable its response to a pending dynamic core voltage change that corresponds to the VID code transition.
2
DSHIFT
3
BSHIFT
4-8
VID[4:0]
9
BOM
10
DPSLP
11
DPRSLP
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PIN FUNCTION DESCRIPTIONS (continued) Pin 12 Mnemonic PWRGD Function Power Good (Active High). This open-drain output pin, via the assistance of an external pull-up resistor to the desired voltage, indicates that the core voltage is within the specified tolerance of the VID programmed value, or else is in a VID transition state as indicated by a recent state transition of either the BOM or DPRSLP pins. PWRGD is deactivated (pulled low) when the IC is disabled, in UVLO Mode, or starting up, or the COREFB voltage is out of the core Power Good window. The open-drain output allows external wired ANDing (logical NORing) with other open-drain/ collector Power Good indicators. Shutdown (Active Low). This is a digital input pin coming from a system signal that, in its active state, shuts down the IC operation, placing the IC in its lowest quiescent current state for maximum power savings. Clamp (Active High). This open-drain output pin, via the assistance of an external pull-up resistor, indicates that the core voltage should be clamped for its protection. To allow the highest level of protection, the CLAMP signal is developed using both a redundant reference and a redundant feedback path with respect to those of the main regulation loop. The signal is timed out using the soft start capacitor, so an external current protection mechanism (e.g., a fuse or ac adapter's current limit) should be tripped within ~3 times the programmed soft start time (e.g., 5 ms~10 ms). In a preferred and more conservative configuration, the core voltage is clamped by an external FET. The initial protection function is served when it is activated by detection of either an overvoltage or a reverse voltage condition on the COREFB pin. Due to loss of the latched signal at IC power-off, backup protection function is served by connecting the pull-up resistor to a system "ALWAYS" regulator output (e.g., V5_ALWAYS). If the external FET is used, this implementation will keep the core voltage clamped until the ADP3203 has power reapplied, thus keeping protection for the CPU even after a hard-failure power-down and restart (e.g., a shorted top or bottom FET). Drive-Low Shutdown (Active Low). In its active state, this digital output pin indicates that the lower FET of the core VR should be disabled. In the suggested application schematic, this pin is directly connected to the pin of the same name on the ADP3415 or other driver IC. Drive-low shutdown is normally activated by the DPRSLP signal corresponding to a light load condition, but a number of dynamic conditions can override the control of this pin as needed. Soft Start. The output of this analog I/O pin is a controlled current source used to charge or discharge an external grounded capacitor; the input is the detected voltage that is indicative of elapsed time. The pin controls the soft start time of the IC as well as the hiccup cycle time during overload, including but not limited to short circuit, overvoltage, and reverse voltage. Hiccup operation was added to reduce short circuit power dissipation by more than an order of magnitude, while still allowing an automatic restart when the failure mode ceased. Core Feedback. This high impedance analog input pin is used to monitor the output voltage for setting the proper state of the PWRGD and CLAMP pins. It is generally recommended to RC-filter the ripple and noise from the monitored core voltage, as suggested by the application schematic. Digital-to-Analog Converter Output. This output voltage is the VID-controlled reference voltage whose primary function is to determine the output voltage regulation point. Ground Output to Driver 1. This digital output pin is used to command the state of the switched node via the driver and MOSFET switches. It should be connected to the IN pin of the ADP3415 driver that corresponds to the first of two channels.
13
SD
14
CLAMP
15
DRVLSD
16
SS
17
COREFB
18 19 20
DACOUT GND OUT1
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PIN FUNCTION DESCRIPTIONS (continued) Pin 21 Mnemonic OUT2 Function Output to Driver 2. This digital output pin is used to command the state of the switched node via the driver. It should be connected to the IN pin of the ADP3415 driver that corresponds to the second of two channels. Current Sense, Channel 1. This high impedance analog input pin is used to provide negative feedback of the current information for the first of two channels. Current Sense, Channel 2. This high impedance analog input pin is used to provide negative feedback of the current information for the second of two channels. The pin is also used to determine whether the chip is acting as a single- or dual-phase controller. If the pin is tied to VCC but not a sense resistor, then the dual-phase operation is disabled; the chip works as a single-phase controller. In this condition, the second phase's output signal (OUT2) does not switch but stays static low. Power Supply. This should be connected to the system's 3.3 V power supply output. Regulation Ramp Feedback Input. The RAMP pin voltage is compared against the REG pin for cycle-by-cycle switching response. Several switched current sources also appear at this input: the cycle-by-cycle hysteresis setting switched current programmed by the HYSSET pin, the BOM shift current programmed by the BSHIFT pin, and the Deep Sleep shift current programmed by the DSHIFT pin. The external resistive termination at this pin sets the magnitude of the hysteresis applied to the regulation loop. Regulation Voltage Summing Input. This is a high impedance analog input pin into which the voltage reference of the feedback loop allows the summing of both the DACOUT voltage and the core voltage for programming the output resistance of the core voltage regulator. This is also the pin at which an optimized transient response can be tailored using Analog Devices' patented ADOPT design technique. Current Limit Positive Sense. This high impedance analog input pin is multiplexed between either of the two current-sense inputs during the high state of the OUT pin of the respective channel. During the common off-time of both channels, the pin's voltage reflects the average of the two channels. The multiplexed current sense signal is passed to the core comparator through an external resistive termination connected from this pin to the RAMP pin. The external (RAMP) resistor sets the magnitude of the hysteresis applied to the regulation loop. Current Limit Negative Sense. This high impedance analog input pin is normally Kelvin connected to the negative node of the current sense resistor(s) via a current-limit programming resistor. A hysteretically controlled current--three times the current programmed at the HYSSET pin--also flows out of this pin and develops a current-limit setting voltage across that resistor, which must then be matched by the inductor current flowing in the current sensing resistor in order to trigger the current limit function. When triggered, the current flowing out of this pin is reduced to two-thirds of its previous value, producing hysteresis in the current limiting function.
22 23
CS1 CS2
24 25
VCC RAMP
26
REG
27
CS+
28
CS-
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Typical Performance Characteristics-ADP3203
10000 NORMAL OPERATING MODE
HIGH
1000
SUPPLY CURRENT - A
UVLO MODE
10
1 SHUTDOWN MODE
0.1
PWRGD
100
LOW
0
20
40 60 TEMPERATURE - C
80
100
0.15
0.10
0.05
0
0.05
0.10
0.15
RELATIVE CORE VOLTAGE - %
TPC 1. Supply Current vs. Temperature
TPC 4. Power Good vs. Relative Core Voltage Variation
1.770 1.765 1.760 +0.85%
100
1.755 1.750 1.745 1.740 -0.85% 1.735 1.730
SOFT START TIME - ms
10
DAC OUTPUT - V
1
FULL SCALE
0.1
0
20
40 60 TEMPERATURE - C
80
100
0.01 0.1
1
10
100
SOFT START CAPACITANCE - nF
TPC 2. DAC Output Voltage vs. Temperature
TPC 5. Soft Start Timing vs. Timing Capacitor
0.620
110 108
NORMALIZED BLANKING TIME - %
0.615 0.610
DAC OUTPUT - V
106 104 102 100 98 96 94 92 90 0 20 40 60 80 100
+7.2mV
0.605 0.600 0.595 7.2mV 0.590 0.585 0.580 0 20 40 60 80 100 AMBIENT TEMPERATURE - C ZERO SCALE
TEMPERATURE - C
TPC 3. DAC Output Voltage vs. Temperature
TPC 6. PWRGD Blanking Time vs. Temperature Normalized to 25C
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V_5S D1 BAR43S V_DC RBST2 2.7 C20 1F 0.1 F BST 10 DRVH 9 SW GND 7 DRVL 6
8
C17 3.3 F
C19 0.1 F
ADP3415
1
C21 . . . C26
6 10 F
IN SD DRVLSD DLY VCC Q9 IR7811W Q10 IR7811W
V_3S
3
2
R4 2.7
4 5
D5 MBRS130LT3
D6 MBRS130LT3
R15 10
C1 0.1 F C2 1F Q6 IR7811W Q7 IR7811W Q8 IR7811W
R4 0
L2 0.32 H
RHYSSET CS- 28 10pF RC 1.5k 1% COC 4700pF C3 C24 0.015 F CS+ 27 REG 26 10pF RA 243 RB OPEN 1% C4 RAMP 25 VCC 24 CS2 23 CS1 22 OUT2 21 OUT1 20 GND 19 DACOUT 18 RCFB 2.7 C8 0.1 F C10 3.3 F C12 0.1 F RBST1 2.7 BST 10 DRVH SW
4 9 8 3
34.0k
ADP3203
RCL 432 1%
RDSHIFT 8.06k
RBSHIFT 19.1k VID4 VID3 VID2 VID1 VID0 BOM CDAC 0.01 F V_5S D1 BAR43S RD 1.05k 1%
1% 1 HYSSET 1% 2 DSHIFT 1% 3 BSHIFT
VR_VID4
4
RSC2 2m VCORE
VR_VID3
5
VR_VID2
6
VR_VID1
7
C40 . . . C45 C25 0.015 F R14 10 RSC1 2m
6 220 F
V_3S
GMUXSEL
VR_VID0 RBOM 220k
8
3k COREFB 17 SS 16 DRVLSD 15 CSS 0.047 F
(IMVP-2 ONLY) STP_CPU
9
10 DPSLP
DPRSLPVR
11 DPRSLP
L1 0.32 H
Figure 1. Typical Application -10-
C20 1F 0.1 F
12 PWRGD
VR_PWRGD
CORE_ON
13 SD
V_DC
14 CLAMP
ADP3415
1 2
C31 . . . C36
6 10 F Q1 IR7811W
IN SD DRVLSD DLY
Q2 IR7811W GND
7
D3 MBRS130LT3
5
D4 MBRS130LT3 VCC DRVL
6
R16 0
V_5 ALWAYS
Q3 IR7811W
Q4 IR7811W
Q5 IR7811W
Q13 IR7807V
R20 5.1K 10%
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THEORY OF OPERATION Overview
Featuring a new proprietary single- or dual-channel buck converter hysteretic control architecture developed by Analog Devices, the ADP3203 is the optimal core voltage control solution for both IMVP-II and IMVP-III generation microprocessors. The complex, multitiered regulation requirements of either IMVP specification are easily implemented with the highly integrated functionality of this controller.
Power Conversion Control Architecture
voltage. The core voltage decreases as a function of load current along the load line, which is synonymous with an output resistance of the power converter. The core voltage is also offset by a dc value--usually specified as a percentage--depending on the operating mode. The voltage offset is also called a "shift." Two pins, BSHIFT and DSHIFT, are used to program the magnitude of the voltage shifts. The voltage shifts are accomplished by injecting current at the node of the negative input pin of the feedback comparator. Resistive termination at the pins determines the magnitude of the voltage shifts. Two other pins, BOM and DPSLP, are used to activate the respective two shifts only in their active low states. In the ADP3203, the shifts are mutually exclusive, with the deep sleep shift (controlled by the DPSLP and DSHIFT pins) being the dominant one. Another pin, DPRSLP, eliminates both shifts only in its active high state. Its assertion corresponds to the Deeper Sleep Operating Mode.
Current Limiting
Driving of the individual channels is accomplished using external drivers, such as the ADP3415. One PWM interface pin per channel, OUT1 and OUT2, is provided. A separate pin, DRVLSD, commands the driver to enable or disable synchronous rectifier operation during the off time of each channel. The same DRVLSD pin is connected to all three drivers. The ADP3203 uses hysteretic control. The resistor from the HYSSET Pin to ground sets up a current that is switched bidirectionally into a resistor interconnected between the RAMP and CS+ pins. The switching of this current sets the hysteresis. In its dual-channel configuration, the hysteretic control requires multiplexing information in all channels. The inductor current of the channel that is driven high is controlled against the upper hysteresis limit. During the common off time of the channels, the inductor currents are averaged together and compared against the lower hysteresis limit. This proprietary off-time averaging technique serves to eliminate a systematic offset that otherwise appears in a fully multiplexed hysteretic control system.
Compensation
The current programmed at the HYSSET pin and a resistor from the CS- pin to the common node of the current sense resistors set the current limit. If the current limit threshold is triggered, a hysteresis is applied to the threshold so that hysteretic control is maintained during a current limited operating mode.
Soft Start and Hiccup
A capacitor from the SS pin to ground determines both the soft start time and the frequency at which hiccup will occur under a continuous short circuit or overload.
System Signal Interface
As with all ADI products for core voltage control, the controller is compatible with ADOPT compensation, which provides the optimum output voltage containment within a specified voltage window or along a specified load line using the fewest possible output capacitors. The inductor ripple current is kept at a fixed programmable value, while the output voltage is regulated with fully programmable voltage positioning parameters, which can be tuned to optimize the design for any particular CPU regulation specification. By controlling the ripple current rather than the ripple voltage, the frequency variations associated with changes in output impedance for standard ripple regulators will not appear.
Feedback/Current Sensing
Accurate current sensing is needed to accomplish output voltage positioning accurately, which, in turn, is required to allow the minimum number of output capacitors to be used to contain transients. A current sense resistor is used between each inductor and the output capacitors. To allow the control to operate without amplifiers, the negative feedback signal is multiplexed from the inductor or upstream side of the current sense resistors, and a positive feedback signal, if needed for load line tuning, is taken from the output or downstream side.
Output Voltage Programming by VID, Offsets, and Load Line
Several pins of the ADP3203 are meant to connect directly to system signals. The VID pins connect to the system VID control signals. The DPRSLP pin connects to the system's DPRSLPVR signal. The DPSLP pin connects to the system's DPSLP or STPCPU signal. The BOM signal connects to the system's GMUXSEL signal. In an IMVP-II system, the GMUXSEL signal precedes any VID code change with a few nanoseconds, while in an IMVP-III system, it follows it with a maximum 12 s delay. To comply with both specifications, the ADP3203 has a VID register in front of the DAC inputs that is written by a short pulse generated at the rising or falling edge of the GMUXSEL signal. In an IMVP-II configuration, if the external VID multiplex settling time is longer than the internal VID register's write pulsewidth, then the insertion of an external RC delay network in the GMUXSEL signal path (in front of the BOM pin) is recommended. The Intel specification calls for maximum 200 ns VID code setup time. This specification can be met with a simple RC network that consists of only a 220 k resistor and no external capacitor, just the BOM pin's capacitance.
Undervoltage Lockout
The ADP3203's supply pin, VCC, has undervoltage lockout (UVLO) functionality to ensure that if the supply voltage is too low to maintain proper operation, the IC will remain off and in a low current state.
Overvoltage Protection (OVP) and Reverse Voltage Protection (RVP)
In the IMVP-II and IMVP-III specifications, the output voltage is a function of both the core current (according to a specified load line) and the system operating mode (i.e., performance or battery optimized, normal or deep sleep clocking state, or deeper sleep). The VID code programs the "nominal" core
The ADP3203 features a comprehensive redundantly monitored OVP and RVP implementation to protect the CPU core against an excessive or reverse voltage, e.g., as might be induced by a component or connection failure in the control or power stage. -11-
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Two pins are associated with the OVP/RVP circuitry--a pin for output voltage feedback, COREFB, which is also used for Power Good monitoring but not for voltage regulation, and an output pin, CLAMP. The CLAMP pin defaults to a low state at startup of the ADP3203 and remains low until an overvoltage or reverse voltage condition is detected. If either condition is detected, the CLAMP pin is switched and latched to the VCC pin. The high state of the CLAMP pin is reset only after several milliseconds as the soft start pin discharges. For maximum and fastest protection, the CLAMP pin should be used to drive the gate of a power MOSFET whose drain source is connected across the CPU core voltage. Detection of overvoltage or reverse voltage will clamp the core voltage to essentially zero, thus quickly removing the fault condition and preventing further energy from being applied to the CPU core. For a less comprehensively protective but also less costly solution, the CLAMP pin may be used to latch the disconnection of input power. The latch should be powered whenever any input power source is present. Typically, such a latching circuit is already present in a system design, so it becomes only a matter of allowing the CLAMP pin to also trigger the latch. In this configuration, the latched off state of the system would be indicative of a system failure. The overvoltage/reverse voltage protective means is via not allowing the continued application of energy to the CPU core. The design objective should be, however, to ensure that the CPU core could safely absorb the remaining energy in the power converter, since this energy is not clamped as in the preferred configuration.
LAYOUT CONSIDERATIONS Advantages in PCB Layout
sided PCB, the best layout would have components aligned in the following order: ADP3415, MOSFETs and input capacitor, output inductor, current sense resistor, output capacitors, control components, and ADP3203. Note that the ADP3203 and ADP3415 are completely separated for an ideal layout, which is impossible with a single-chip solution. This keeps the noisy switched power section isolated from the precision control section and gives more freedom in the layout of the power switching circuitry. 2. Whenever a power dissipating component (e.g., a power MOSFET) is soldered to a PCB, the liberal use of vias, both directly on the mounting pad if possible and immediately surrounding it, is recommended. Two important reasons for this are: improvement of the current rating through the vias (if it is a current path) and improved thermal performance, especially if there is opportunity to spread the heat with a plane on the opposite side of the PCB.
Power Switching Circuitry ADP3415, MOSFETs, and Input Capacitors
3. Locate the ADP3415 near the MOSFETs so that the loop inductance in the path of the top gate drive returned to the SW pin is small, and similarly for the bottom gate drive whose return path is the ground plane. The GND pin should have at least one very close via into the ground plane. 4. Locate the input bypass MLC capacitors close to the MOSFETs so that the physical area of the loop enclosed in the electrical path through the bypass capacitor and around through the top and bottom MOSFETs (drain source) is small and wide. This is the switching power path loop. 5. Make provisions for thermal management of all the MOSFETs. Heavy copper and wide traces to ground and power planes will help to pull the heat out. Heatsinking by a metal tap soldered in the power plane near the MOSFETs will help. Even just a small airflow can help tremendously. Paralleled MOSFETs to achieve a given resistance will help spread the heat. 6. An external Schottky diode (across the bottom MOSFET) may increase efficiency by a small amount (< ~1%), depending on its forward voltage drop compared to the MOSFET's body diode at a given current; a MOSFET with a built-in Schottky is more effective. For an external Schottky, it should be placed next to the bottom MOSFET or it may not be effective at all. 7. The VCC bypass capacitor should be close to the VCC pin and connected on either a very short trace to the GND pin or to the GND plane.
Output Filter Output Inductor and Capacitors, Current Sense Resistor
This 2-phase solution separates the controller (ADP3203) and the MOSFET drivers (ADP3415). Today, most motherboards only leave small pieces of PCB area for the power management circuit. Therefore, the separation of the controller and the MOSFET drivers gives much greater freedom in layout than any single chip solution. Meanwhile, the separation also provides the freedom to place the analog controller in a relatively quiet area in the motherboard. This can minimize the susceptibility of the controller to injected noise. Any single-chip solution with a high speed loop design will suffer larger susceptibility to jitter that appears as modulation of the output voltage. The ADP3203 maximizes the integration of IMVP-III features. Therefore, no additional externally implemented functions are required to comply with IMVP-III specifications. This saves PCB area for component placement on the motherboard.
PCB Layout Consideration for ADP3203/ADP3415
The following guidelines are recommended for optimal performance of the ADP3203 and ADP3415 in a power converter. The circuitry is considered in three parts: the power switching circuitry, the output filter, and the control circuitry.
Placement Overview
8. Locate the current sense resistors very near to the output voltage plane. 9. The load-side heads of sense resistors should join as closely as possible for accurate current signal measurement of each phase. 10. PCB trace resistances from the current sense resistors to the regulation point should be minimized, known (calculated or measured), and compensated for as part of the design if it is significant. (Remote sensing is not sufficient
1. For ideal component placement, the output filter capacitors will divide the power switching circuitry from the control section. As an approximate guideline considered on a single-
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for relieving this requirement.) A square section of 1-ounce copper trace has a resistance of ~500 that adds to the specified dc output resistance of the power converter. The output capacitors should similarly be close to the regulation point and well tied into power planes as impedance here will add to the ac output resistance (i.e., the ESR) that is implicitly specified as well. 11. Whenever high currents must be routed between PCB layers, vias should be used liberally to create parallel current paths so that the resistance and inductance are minimized and the via current rating is not exceeded.
Control Circuitry ADP3203, Control Components APPLICATION INFORMATION Theoretical Background
This application section presents the theoretical background for multiphase dc-to-dc converters using the ADP320x family of controllers for mobile CPUs. Members of that family control multiphase ripple regulators (also called hysteretic regulators) in a configuration that allows employing ADOPT, Analog Devices' optimal voltage positioning technique, to implement the desired output voltage and load line both statically and dynamically, as required by Intel's IMVP-II and IMVP-III specifications.
Single-Phase Hysteretic Regulator with ADOPT
12. If the ADP3203 cannot be placed as previously recommended, care should be taken to keep the device and surrounding components away from radiation sources (e.g., from power inductors) and capacitive coupling from noisy power nodes. 13. Noise immunity can be improved by the use of a devoted signal ground plane for the power controller and its surrounding components. Space for a ground plane might readily be available on a signal plane of the PCB since it is often unused in the vicinity of the power controller. 14. If critical signal lines (i.e., signals from the current sense resistor leading back to the ADP3203) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals. 15. Absolutely avoid crossing any signal lines over the switching power path loop, described previously. 16. Accurate voltage positioning depends on accurate current sensing, so the control signals that monitor the voltage differentially across the current sense resistor should be Kelvin-connected. Please refer to the ADI Evaluation Board of the ADP3203 and its documentation for control signal connection with sense resistors. 17. The RC filter used for the current sense signal should be located near the control components as this serves the dual purpose of filtering out the effect of the current sense resistors' parasitic inductance and the noise picked up along the routing of the signal. The former purpose is achieved by having the time constant of the RC filters approximately matched to that of the sense resistors and is important for maintaining the accuracy of the current signal.
Figure 2 shows the conventional single-phase hysteretic regulator and the characteristic waveforms. The operation is as follows. During the time the upper transistor, Q1, is turned on, the inductor current, IL, and also the output voltage, VOUT, increase. When VOUT reaches the upper threshold of the hysteretic comparator, Q1 is turned off, Q2 is turned on, and the inductor current and the output voltage decrease. The cycle repeats after VOUT reaches the lower threshold of the hysteretic comparator.
VIN Q1 VSW Q2 VOUT VH L IL CO RE + LOAD VOUT VSW
t
t
VH VREF IL
t
Figure 2. Conventional Hysteretic Regulator and Its Characteristic Waveforms
Since there is no voltage error amplifier in the hysteretic regulator, its response to any change in the load current or the input voltage is virtually instantaneous. Therefore, the hysteretic regulator represents the fastest possible dc-to-dc converter. A slight disadvantage of the conventional hysteretic regulator is that its frequency varies with the input and output voltages. In a typical mobile CPU converter application, the worst-case frequency variation due to the input voltage variation is in the order of 30%, which is usually acceptable. In the simplest implementation of the hysteretic converter, shown in Figure 2, the frequency also varies proportionally with the ESR, RE, of the output capacitor. Since the initial value is often poorly controlled, and the ESR of electrolytic capacitors also changes with temperature and age, practical ESR variations can easily lead to a frequency variation in the order of three to one. However, a modification of the hysteretic topology eliminates the dependence of the operating frequency on the ESR. In addition, the modification allows the optimal implementation, ADOPT, of Intel's IMVP-II and IMVP-III load line specifications. Figure 3 shows the modified hysteretic regulator.
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ADP3203
VIN Q1 VSW Q2 L IL COC RCS CO RC RD VH VREF RE + LOAD VOUT
COC, which effectively couples the ac component of the output voltage to the noninverting input voltage of the comparator. Since the comparator sees only the ac voltage across RCS, in the circuit of Figure 3 the dependence of the switching frequency on the ESR of the output capacitor is completely eliminated. Equation 4 presents the expression for the switching frequency.
Figure 3. Modified Hysteretic Regulator with ADOPT
f=
RCS (VIN - VOUT )VOUT LVH VIN
(4)
The implementation requires adding a resistive divider (RC and RD) between the reference voltage and the output and connecting the tap of the divider to the noninverting input of the hysteretic comparator. A capacitor, COC, is placed across the upper member (RC) of the divider. It is easily shown that the output impedance of the converter can be no less than the ESR of the output capacitor. A straightforward derivation demonstrates that the output impedance of the converter in Figure 3 can be minimized to equal the ESR, RE, when the following two equations are valid (neglecting PCB trace resistance for now):
RD RE - RCS = RC RCS
Multiphase Hysteretic Regulator with ADOPT
(1)
and COC = CO R2 E RCS RD (2)
Multiphase converters have very important advantages, including reduced rms current in the input filter capacitor (allowing the use of a smaller and less expensive device), distributed heat dissipation (reducing the hot-spot temperature and increasing reliability), higher total power capability, increased equivalent frequency without increased switching losses (allowing the use of a smaller equivalent inductances, and thereby shortening the load transient time), and reduced ripple current in the output capacitor (reducing the output ripple voltage and allowing the use of a smaller and less expensive output capacitor). Also, they have some disadvantages, which should be considered when choosing the number of phases. Those disadvantages include the need for more switches and output inductors than in a single-phase design (leading to a higher cost than a single-phase solution, at least below a certain power level), more complex control, and the possibility of uneven current sharing among the phases. The family of ADP320x controllers alleviates two of the above disadvantages of multiphase converters. It presents a simple and cost-effective control solution and provides perfect current sharing among the phases. Figure 4 shows a simplified block diagram of a 3-phase converter using the control principle implemented with the ADP3203, the 3-phase member of the ADP320x family. As Figure 4 shows, in the multiphase configuration the ripple current signal is multiplexed from all channels. During the on time of any given channel, its current is compared to the upper threshold of the hysteretic comparator. When the current reaches the upper threshold, the control FET of that channel is turned off. During the common off time of all channels, their currents are averaged and compared to the lower threshold. When the averaged channel current reaches the lower threshold, the hysteretic comparator changes state again and turns on the control FET of the next channel, as selected by the phase
From Equation 2, the series resistance is:
RCS =
RE R 1+ D RC
(3)
This is the ADOPT configuration and design procedure that allows the maximum possible ESR to be used while meeting a given load line specification. It can be seen from Equation 3 that unless RD is zero or RC is infinite, RCS will always be smaller than RE. An advantage of the circuit of Figure 3 is that if we select the ratio RD/RC well above unity, the additional dissipation introduced by the series resistance RCS will be negligible. Another interesting feature of the circuit in Figure 3 is that the ac voltage across the two inputs of the hysteretic comparator is now equal only to the ac voltage across RCS. This is due to the presence of the capacitor
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splitter logic. This control concept ensures that the peak currents of all channels will be the same, and therefore the channel currents will be perfectly balanced. The ADOPT compensation can be used the same way as in the single-phase version discussed in the preceding text. Since due to second order effects, the detailed design of a multiphase converter with the ADP320x family is rather complex, a design aid using MathSoft's MathCAD(R) program has been developed. Please contact ADI for further information.
Q1 VIN
VSW1 Q2
PHASE 1
L1
IL1
RCS1
Q3
VOUT VSW2 PHASE 2 L2 IL2 RCS2 RE CO Q4 LOAD
PHASE SPLITTER OUT 2 OUT 1
HYSTERETIC CORE COMPARATOR
CURRENT SENSE MUX CS1 VH CS2 COC RC
RD VREF
Figure 4. 2-Phase Modified Hysteretic Regulator with ADOPT
MathCAD is a registered trademark of MathSoft Engineering & Education, Inc.
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OUTLINE DIMENSIONS 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28)
C02839-0-7/02(0)
8 0 0.75 0.60 0.45
Dimensions shown in millimeters
9.80 9.70 9.60
28
15
4.50 4.40 4.30
1 14
6.40 BSC
PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 1.20 MAX
COPLANARITY 0.10
SEATING PLANE
0.20 0.09
COMPLIANT TO JEDEC STANDARDS MO-153AE
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PRINTED IN U.S.A.

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